Title: Traveling Threads: A New Multi-Threaded Execution Model

Speaker: Richard C. Murphy, Notre Dame University

Date/Time: Monday, April 11, 2005, 2:00-3:00 pm

Location: Building 980, Room 95 (Sandia NM)

Brief Abstract: The primacy of single processor performance, and the ease of the corresponding programming model, has forced the architects of parallel machines to accept limited scalability of processor and memory hierarchies.  While architectures at any scale are plagued by the von Neumann bottleneck, the upcoming generation of trans-petaflop machines represent the hardest scalability problem.  While interconnection networks provide more bandwidth, they have done little to address the problem of relative latency.  In a typical machine that includes both near (on-node) and far (off-node) memory, both types of memory are relatively more distant from the processing resources.  Furthermore, finding the concurrency in existing instruction streams to mask that latency is an increasingly daunting task.  Advances in architecture are required to address this problem.

This work presents a new multi-threaded execution model based on architecture-level thread migration that combats both the problem of providing additional concurrency (to mask latency) and reducing interconnection network pressure (by converting request-reply operations to one-way operations).  The architectural parameters of this model are analyzed in the context of a set of Sandia benchmarks (CTH, LAMMPS, sPPM, and a driver for Trilinos).  Furthermore, the fundamental properties of the Sandia codes are assessed in relation to the SPEC Floating Point Benchmark Suite (SPEC-FP), the gold standard for computer architecture research.  It will be shown that the Sandia codes exhibit significantly more memory activity than their SPEC-FP counterparts.