Title: Hardened by Design Approaches for Mitigating Transient Faults in Memory-Based Systems

Speaker: Daniel Blum, Washington State University

Date/Time: Wednesday, June 20, 2007, 10:30am - 11:30am

Location: CSRI Building, Room 90 (Sandia NM)

Brief Abstract: In the presence of radiation, particle strikes can induce transient errors in integrated circuits (ICs). Strikes directly disrupting memory are known as Single Event Upsets (SEUs), while strikes initially disrupting logic are called Single Event Transients (SETs). Chips manufactured in aggressive technologies that operate in highly radioactive environments may also experience particle strikes that induce Multiple Bit Upsets (MBUs). This research focuses on novel hardened by design circuit-level approaches to protecting integrated circuits against SEUs, SETs and MBUs. A number of system-level designs have been developed utilizing these approaches to demonstrate their capabilities.
           
Many of the design-hardened memory circuits considered in this study share a common theme, which is the ability to bypass transient faults. This is critical for performance, as it allows a digital system to proceed with subsequent operations while one of its memory cells is recovering from a disruption. Among the considered bypass-capable approaches, the novel Triple Path DICE (TPDICE) structure is the most balanced. This structure is utilized in a number of digital system applications, including an SEU and SET-tolerant reconfigurable digital signal processing (DSP) architecture, SEU and SET-tolerant pipeline memory circuits, and an MBU-tolerant memory design. These applications demonstrate the ability of hardened by design memory to achieve SEU and SET tolerance in memory transfer and combinational logic based systems, as well as in harsh radioactive environments.

CSRI POC: James A. Ang, (505) 844-0068