Title: Low Power, Radiation-hardened Sequential Circuit Technique for Radiation-hardened Process
Speaker: John K. McIver, III, Micro-RDC
Date/Time: Friday, August 8, 2008, 10:00 am
Location: CSRI Building, Room 90 (Sandia NM)
Brief Abstract: A novel low-power radiation-hardened sequential digital circuit which supports multiple supply voltages, integrated logic, and a low-power stand-by state is presented. The design is rigorously analyzed for performance against ion strikes, power, and speed.
The design is targeted for a radiation-hardened process; it guarantees radiation immunity by use of proven radiation-hardened circuit techniques.
The circuit is based on differential cascade voltage switch logic, which provides an integral level shift and allows storage at the full supply voltage supported by the process, while allowing the combinational logic supply voltage to scale for power savings. This design is compared to a production baseline radiation-hardened flip-flop. For an activity factor of 10% and 1.4 V clock and combinational logic level, the power energy per clock is reduced over 80% compared to the baseline radiation-hardened flip-flop, while maintaining the same radiation-hardness.
CSRI POC: Jim Ang, (505) 844-0068 |