Title: Modeling the Manufacturing Imperfection in IC Design Flow

Speaker: Zhenhai Zhu, Massachusetts Institute of Technology

Date/Time: Monday: September 28, 2009 at 10:00 am         

Location: CSRI Building, Room 90 (Sandia NM)

Brief Abstract: Manufacturing imperfection in steps like lithography and chemical
mechanical polishing is a fact of life in IC fabrication. Two approaches have been used to improve the yield. The first approach is to reduce the imperfection. Resolution enhancement technique in lithography is a good example. But this typically involves computationally intensive modeling and simulation. The second approach is to reduce the venerability of the circuits to the imperfection. Design guard band is an effective technique, but could result in poorer designs due to larger area and longer routed wires.  Variation-aware timing methodology has been used to make trade-off between yield and performance. In this talk I will cover our recent research on both fronts.

The first part of the talk focuses on lithography simulation. I will first give a brief tutorial on lithography simulation. I will then explain the key ideas used in an innovative parametric lithography simulation method based on parametric Finite Element Method.
Numerical results show that the new method is 1500 times faster than the standard FEM. In addition, smooth trade-off between efficiency and accuracy can be easily made to suit the needs of different designs.

 The second part of the talk focuses on the variation-aware timing analysis. I will present the contributions we have made in the parametric model order reduction and the parasitic extraction based on fast integral equation solvers.

CSRI POC: Robert Hoekstra, (505) 844-7627