Title: Microarchitecture Research and Design Challenges in the
Multicore Era

Speaker: Clayton Hughes, Department of Electrical and Computer Engineering, University of Florida

Date/Time: Monday, November 1, 2010, 10:00 a.m.       

Location: CSRI Building/Room 90 (Sandia NM)

Brief Abstract: As single core processor performance stagnated with systems hitting the limits of instruction-level parallelism (ILP) and physical constraints, computer architects turned to chip multiprocessors (CMPs) as a path toward maintaining previous performance trends. The design and evaluation of these systems is a difficult and time-consuming process driven by rigorous testing. Identifying design tradeoffs and optimizing for both power and performance increases the design space and the multiple interactions possible in multicore architectures is likely to increase simulation time. Moreover, taking advantage of the additional resources offered by CMPs means a shift in application development to explicitly parallel programs. Multithreaded applications running on multicore systems add additional layers of complexity for system designers as well as software developers.

In this work, new tools for accurate multithreaded workload synthesis for both lock- and transactional memory-based programs are developed. These tools can derive new benchmarks from existing ones while reducing simulation time. Moreover, they provide a means for developing entirely new benchmarks that can stress systems in unique ways. These new benchmarks can significantly accelerate and extend architecture design evaluations of multicore processors and hardware transactional memory systems.
The remainder of the work addresses the problem of power. At the chip level, power consumption can affect its reliability and performance and can increase packaging and manufacturing costs. While CMPs offer better energy efficiency than previous uniprocessors, they still suffer from the same heat removal problems as previous generations. However, unlike previous generations, CMPs provide more opportunities for balancing energy use. An analysis of the per-core and chip-wide power consumption of hardware transactional memory systems (HTMs) pinpoints two areas ripe for power management policies: transactional stalls and aborts. By applying dynamic voltage and frequency scaling (DVFS) and intelligent scheduling, the power-performance of HTMs improves significantly.

CSRI POC: Jim Ang, 505-844-0068