Title: Hardware Acceleration for Conservative Parallel Discrete Event Simulation on Multi-Core Systems Speaker: Elizabeth Lynch, Georgia Institute of Technology Date/Time: Tuesday, May 18, 20109:00 – 10:00 a.m. Location: CSRI Building/Room 90 (Sandia NM) Brief Abstract: Multi-core architectures are becoming more common and core counts continue to increase. There are six- and eight-core chips currently in production, such as Intel Gulftown, and many-core chips with dozens of cores, such as the Intel Teraflops 80-core chip, are projected in the next five years. However, adding more cores often does not improve the performance of applications. We want to take advantage of the multi-core environment to speed up parallel discrete event simulation. The current bottleneck for many parallel simulations is time synchronization. This is especially true for simulations of wireless networks and on-chip networks, which have low look ahead. Message passing is also a common simulation bottleneck. We have designed hardware at a functional level that performs the time synchronization for parallel discrete event simulation asynchronously and in just a few clock cycles, eliminating the need for global communication with message passing or lock contention for shared memory. This hardware, which we call the Global Synchronization Unit, consists of 3 register files, each the size of the number of cores, and is accessed using 5 new atomic instructions. We have conducted an initial performance study using simulation, and determined that for up to 8 cores our hardware unit reduces the runtime of a low-lookahead parallel network simulation by 50% over a shared-memory implementation of synchronization. Although we have yet to determine how long these atomic instructions will take to execute, we have shown that even if they take hundreds of cycles each, there will still be a significant performance improvement over a shared-memory implementation.CSRI POC: Arun Rodrigues, 505-284-6090 |