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Collected 2009 Presentations
Where the author has given permission, the titles for Wedndesday and Thursday talks are hyperlinks to the presentation documents. Where this has not been possible, there is often a parenthetical note explaining why.
| Richard Berger |
BAE Systems |
Interoperability of Standard Interfaces within a Spaceborne Computer |
| Mike Deliman |
Wind River Systems |
SMP/AMP Multicore Enhancements, Hypervisor, Disrutpion Tolerant Networking, Deep Impact Probe, and InterPlanetary Internet |
| John DeMello |
Air Force Research Labs |
Warfighter Requirements and the Need for On-Board Processing |
| Daniel Dvorak |
Jet Propulsion Laboratory/Caltech |
Managing Complexity through Architecture |
| Mitch Fletcher |
Honeywell |
Progression of an Open Architecture:from Orion to Altair and LSS
[presentation] [paper] |
| Yutao He |
Jet Propulsion Laboratory |
ISAAC – Highly-Reusable, Highly-Capable, Integrated Instrument Computing and Control Platform |
| Bob Hodson |
NASA Langley Research Center |
Fault Tolerant Computing for Exploration |
| Ken Hunt |
SEAKR |
Space Electronics: Computing and More |
| AJ Kleinosowski |
Boeing |
OPERA Overview: On-board Processing Expandable Reconfigurable Architecture (OPERA) Program |
| Peter Kogge |
Boeing |
Exascale Computing: Embedded Style |
| Rob Lampereur |
Ball Aerospace |
Kepler Fault Protection and its Applicability to Multi-Core |
| Richard Lethin |
Reservoir Labs |
Auto Kernel Mapping to Spaceborne Computer Architectures using R-Stream Compiler and Results |
| Bill Lundgren |
Gedae, Inc. |
Gedae: Software-Enabled Systems Engineering Facilitates Certification of New Platforms |
| Mike Malone |
Draper Laboratory |
OPERA Intellectual Property |
| Ken Prager |
Ratheon |
Introduction: Monarch Processor |
| Ken Prager |
Ratheon |
Monarch: A High Performance Signal Processing Building Block for Space Computing |
| Heather Quinn |
Los Alamos National Laboratory |
Reliability Modeling Tools for Improving Space System Design: Case Studies and Results |
| Kirk Reinholtz |
Jet Propulsion Laboratory |
Mission Data System |
| Rick Ridgley |
ODN/NRO |
R&D Roadmaps to Address
Next Generation Spaceborne Computing |
| John Samson |
Honeywell Aerospace |
Dependable Multiprocessor (DM) Architecture for Space Applications |
| Abstract: The NASA New Millennium Program (NMP) Space Technology 8 (ST8) Dependable Multiprocessor (DM ) project is the current incarnation of the long-held DoD and NASA desire to migrate high-performance COTS supercomputing to space. Many DM system concepts are based on related technologies developed and demonstrated over the past three decades on several DARPA (Defense Advanced Research Projects Agency), NASA, and DoD programs including Space Touchstone, Remote Exploration and Exploration (REE), and Improved Space Architecture Concept (ISAC). The Dependable Multiprocessor (DM) is a processing system embodying an architecture and a methodology which enable COTS-based, high performance, scalable multi-computer systems to operate in space environments. DM technology encompasses fault tolerance middleware which manages a cluster of high performance COTS processors while providing enhanced SEU-tolerance, and supports MPI (Message Passing Interface) parallel and distributed processing. The goals of the DM project were to develop technology that is transparent to the underling platform, able to support upgrades in both hardware and software, and is easy to port applications from the laboratory to space. Over the past 4 years, DM has been demonstrated to be technology-independent and easy to use, not only for parallel and distributed applications, but also for user-selectable SEU-tolerant modes of operation. DM technology has been successfully demonstrated with heterogeneous COTS processors, heterogeneous COTS operating systems (VxWorks and Linux), several state-of the-art multicore processors, and FPGAs. The high speed interconnect between COTS data processing nodes in the DM testbeds is TCP/IP over Ethernet, but the physical interconnect medium could also be parallel or serial RapidIO or wireless. This presentation provides an overview of DM technology and the status of DM's TRL6 technology validation. |
| Warren Snapp |
ODN/NRO |
IP Position Statement |
| Richard Stempien |
The MITRE Corporation |
Fault-Tolerant Spaceborne Computing Employing New Technologies
2009 Conference; Architecture Working Group - May 29, 2009 |
| Ian Troxel |
SEAKR Engineering, Inc. |
Concepts for Plug and Play Spacecraft Bus Payload Architectures |
| Ian Troxel |
SEAKR Engineering, Inc. |
Leveraging COTS to Develop Standard Space Architectures |
| Abstract: The space computing industry is a niche market with specialized needs that has too often developed custom architecture solutions for subsequent missions, even while attempting to use standardized components. Reinventing the wheel has typically proven costly, especially if the "wheel" isn't compatible with "vehicles" thriving with much support in commercial/commodity markets. Standards-based approaches to space hardware development have made a successful impact on system architecture designs, most notably commercial backplane technologies. However, simultaneously, numerous standardization efforts have failed for various reasons such as institutional resistance, design incompatibilities, technology maturity level insufficient, scope too broad or too narrow, rapid obsolescence, etc. There is a continuing goal to establish standards within the industry to reduce cost, risk and schedule but history teaches that there are potential pitfalls along the road to the standardized processing architecture for space.
This talk proposes a context within which the space industry should consider standardization and provides recommendations based on lessons learned from the industry's scrap-heap of failed standardization efforts. The talk will also include a brief overview of SEAKR's architecture methodology and examples of how standardized COTS hardware and tools have been leveraged to develop flexible architectures that target multiple missions. |
| Danny Wilkin |
Aeroflex |
UT699 32-bit Fault-Tolerant LEON 3FT/SPARC™ V8 Processor |
| Hans Zima |
Jet Propulsion Laboratory |
Introspection-based adaptive fault tolerance |
| Hans Zima |
Jet Propulsion Laboratory |
Towards High Productivity Languages for Reliable Flight Computing |
Contact: Erik DeBenedictis
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