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DENIS MAMALUY

This is an old site that will not be updated. My new web-site can be found here:
  • Mamaluy, Denis

  • EDUCATION

    • B. Verkin Institute for Low Temperature Physics & Engineering,Ph.D. in Physics and Mathematics, Kharkov, Ukraine, November 2000.
    • Kharkov State University, Physics Department, division of theoretical physics,M.S. in Physics (with honors), Kharkov, Ukraine, June 1997.
    • UNESCO at Kharkov University,M.A. in Philosophy of Communications and Management, Kharkov, Ukraine, May 1997.

     

    APPOINTMENTS

    2012-pres.: Senior R&D scientist and engineer, Sandia National Laboratories
    2006-2011: Research assistant professor, ECEE, ASU
    2005-2006: Faculty research associate, ECEE, ASU
    2002-2005: Research associate, Department of Electrical Engineering, ASU
    2000-2002: Post-doctorate fellow, Walter Schottky Institute, Technische Universität München, Munich, Germany

     

    PRINCIPAL AREAS OF RESEARCH

    • Computational nanoelectronics
    • Physical limits of computation
    • Quantum transport simulation in nano-structures and nano-devices
    • Efficient numerical algorithms for non-equilibrium Keldysh Green’s function formalism,
      Contact Block Reduction (CBR) method
    • Semiconductor device modeling, nano-device optimization and process variation analysis
    • FinFETs, MuGFETs, SETs, transition-metal-oxide memristors
    • Surface polaritons in dielectrics and ferroelectrics induced by magneto-electric interactions

     

    COMPUTER AND COMPUTATIONAL SCIENCE

    • 20+ years of programming experience:
      • Fortran (all flavors), C++, C, Pascal, Delphi, VBasic, VB script, .NET
      • Maple, Mathematica, Matlab
    • Management and development of quantum transport simulators “CBR2D” and “CBR3D” for nano-transistor optimization and process variation analysis
    • Development of Sandia’s continuum charge transport code, Charon 2.0 TCAD
    • Expertise in numerical methods, including large-scale eigenvalue problems and sparse linear system problems, high-effiency numerical libraries (ARPACK, FEAST), sparse linear system solvers (PARDISO, ILUPACK), Intel’s MKL, AMD’s ACML.
    • Experience with TCAD (both process and device simulation) tools; experience teachingthe corresponding graduate level class “Semiconductor Device and Process Simulations”.
    • Experience in parallel programming using Open MP, MPI
    • Significant practical experience in multi-platform (Linux, Windows, x86, x64) scientific code preparation, compilation and optimization
    • Computer system administration:
      • Linux (workstation level), Windows (workstation and server levels)
      • Installation and administration of MS Exchange Server at Walter Schottky Institute (TU Munich) with over 200 accounts, Windows Active Directory administration (J-script, VB Script).

     

    TEACHING

    • Undergraduate classes
      • Spring semester 2010, ASU, EEE 241 “Fundamentals of Electromagnetics”, (student evaluation1 : 4.9 of 5.0)
      • Fall semester 2010, ASU, EEE 241 “Fundamentals of Electromagnetics” (student evaluation: 4.7 of 5.0)
      • Spring semester 2011, ASU, EEE 120 “Digital Design Fundamentals” (student evaluation: 4.6 of 5.0)
      • Substitute teaching for EEE202 “Circuits”, EEE 436 “Fundamentals of Solid State Devices”.
    • Graduate classes
      • Fall semester 2005, ASU, EEE 533 “Semiconductor Device and Process Simulations” (student evaluation: 4.67 of 5.0)
      • Invited lectures on “Quantum mechanics”, “Semiconductor transport”, “Electron transport in nanostructures”, “Advanced device modeling and simulation”.

     


    1Detailed results of Student Evaluations are available.

     

    RESEARCH PUBLICATIONS

     

    FIVE RECENT SIGNIFICANT PUBLICATIONS IN REFEREED ARCHIVAL JOURNALS

    1. On the Impossibility of a “Pure” Resistance Measurement: The Charge Pileup Model», N. Zimmerman, D. Mamaluy, Phys. Rev. B 82, 115333 (2010).
    2. “Simulation of the Impact of Process Variation on the Optimized 10-nm FinFET”, H. Khan, D. Mamaluy, D. Vasileska, IEEE Trans El. Dev. 55, pp. 2134-2141 (2008).
    3. “Approaching Optimal Characteristics of 10 nm High Performance Devices: a Quantum Transport Simulation Study of Si FinFET”, H. Khan, D. Mamaluy and D. Vasileska, IEEE Trans El. Dev. 55, pp. 743-753 (2008).
    4. "Quantum Transport Simulation of Experimentally Fabricated Nano-FinFET", H. Khan, D. Mamaluy, D. Vasileska, IEEE Tran. El. Dev. 54, pp. 784-796 (2007).
    5. “Contact block reduction method for ballistic transport and carrier densities of open nanostructures”, D. Mamaluy, M. Sabathil, T. Zibold, D. Vasileska, P. Vogl,
      Phys. Rev. B 71, 245321 (2005).

     

    FIVE OTHER SIGNIFICANT PUBLICATIONS IN REFEREED ARCHIVAL JOURNALS

    1. Efficient method for the calculation of ballistic quantum transport”, D. Mamaluy, M. Sabathil, P. Vogl, J. App. Phys. 93, 4628 (2003).
    2. Strong nonreciprocity of phonon polaritons of insulator at its boundary with ideal metal or superconductor in magnetic field”, I. E. Chupis and D. A. Mamaluy, J. Phys.: Condensed Matter 12, 1413 (2000).
    3. Surface polaritons in a dielectric at its boundary with a metal in crossed electric and magnetic field”, D. A. Mamaluy and I. E. Chupis, JETP 90, 153 (2000).
    4. Rectification of surface polaritons in a dielectric at its boundary with a metal in magnetic field”, I. E. Chupis and D. A. Mamaluy, Low Temp. Phys. 25, 833 (1999).
    5. Surface polaritons in  a  dielectric in  constant electric field  at  the  boundary with  a  metal”, I. E. Chupis and D. A. Mamaluy, JETP Letters 68, 922 (1998).

     

    OTHER PUBLICATIONS IN REFEREED ARCHIVAL JOURNALS

    1. “Efficient self-consistent quantum transport simulator for quantum well devices”, Xujiao Gao, Denis Mamaluy, et al., J. Comp. El. (to be published, 2013).
    2. “3D NEGF quantum transport simulator for modeling ballistic transport in nano FinFETs”, H. R. Khan, D. Mamaluy and D. Vasileska, J. Phys.: Conf. Ser. 107, pp. 1-13 (2008).
    3. “Fully  3D  self-consistent quantum transport simulation of  Double-gate and  Tri-gate 10  nm FinFETs”, H. Khan, D. Mamaluy and D. Vasileska, J. Comp. El. 7, pp. 346-349 (2008).
    4. “Can Silicon FinFETs Satisfy ITRS Projections for High Performance 10 nm Devices?”, H. Khan, D. Mamaluy and D. Vasileska, J. Comp. El. 7, pp. 284-287 (2008).
    5. “Influence of Interface Roughness on Quantum Transport in Nano-Scaled FinFET”, H. Khan, D. Mamaluy and D. Vasileska, J. Vac. Sci. Technol. B 25, pp. 1437-1440 (2007).
    6. “Assessment of the CBR quantum transport simulator on Experimentally fabricated nano- FinFET", H. Khan, D. Mamaluy and D. Vasileska, ECS Transactions, Vol. 6(4), pp. 197-203 (2007).
    7. “Self-consistent Treatment of Quantum Transport in 10 nm FinFET Using Contact Block Reduction (CBR) Method”, H. Khan, D. Mamaluy, D. Vasileska, J. Comp. Electronics 6, pp. 77-80 (2007).
    8. “3D quantum transport simulator for next generation devices”, D. Mamaluy, H. Khan and D.Vasileska, J. Phys.: Conf. Ser. 38, pp. 196-199 (2006).
    9. “Ballistic Quantum-Mechanical Simulation of 10nm FinFET Using CBR Method“, H. Khan, D. Mamaluy, D. Vasileska, J. Phys.: Conf. Ser. 38, 200 (2006).
    10. "Calculation of carrier transport through quantum dot molecules", T. Zibold, M. Sabathil, D. Mamaluy, and P. Vogl, AIP Conf. Proc. 722, 799 (2005).
    11. “Contact block reduction method and its application to 10-nm MOSFET device”, D. Mamaluy, D. Vasileska, M. Sabathil, P. Vogl, Semicond. Sci. and Technol. 19, S118 (2004).
    12. “Electron density calculation using the contact block reduction method”, D. Mamaluy, A. Mannargudi, D. Vasileska, J. Comp. Electronics 3, 45 (2004).
    13. “Efficient Computational Method for Ballistic Currents and Application to Single Quantum Dots”, M. Sabathil, S. Birner, D. Mamaluy and P. Vogl. J. Comp. Electronics 2, pp. 269-275 (2004).
    14. “Prediction of realistic quantum logic gate using the contact block reduction method”, M. Sabathil, D. Mamaluy, P. Vogl, Semicond. Sci. and Technol. 19, S137-S140 (2004).
    15. “Influence of dynamic magnetoelectric interaction on surface polaritons in ferroelectrics”, I.E.Chupis and D. A. Mamaluy, Low Temp. Phys. 24, 762 (1998).

     

    REVIEW PAPERS AND BOOK CHAPTERS

    • “Quantum Transport in Nanoscale Devices”, D. Vasileska, D. Mamaluy, I. Knezevic, H. R. Khan, and S. M. Goodnick in Encyclopedia of Nanoscience and Nanotechnology, Edited by H. S. Nalwa, American Scientific Publishers, Los Angeles (2010).
    • “Semiconductor device modeling" (review article), D. Vasileska, D. Mamaluy, H. R. Khan, K. Raleva, and S. M. Goodnick, Journal of Computational and Theoretical Nanoscience Vol. 5, pp. 999–1030 (2008).

     

    Other Publications

    1. Virtual Journal of Nanoscale Science & Technology (August 13, 2007) “Influence of Interface Roughness on Quantum Transport in Nano-Scaled FinFET”, H. Khan, D. Mamaluy [http://www.vjnano.org/]
    2. Nanotech 2006: Technical Proceedings of the 2006 NSTI Nanotechnology Conference and Trade Show, Volume 1, "Self-consistent Quantum Mechanical Treatment of the Ballistic Transport in 10 nm FinFET Devices Using CBR Method", D. Mamaluy, K. Khan, D. Vasileska, pp. 54-307 (2006).
    3. Nextnano3 – a state-of-the-art simulation tool for 3D quantum nanodevices”,
      S. Birner, S. Hackenbuchner, J.A. Majewski, D. Mamaluy, M. Sabathil, G. Zandler
      Annual Report 2001, Walter Schottky Institute, TU Munich (2002)
      [http://www.wsi.tu-muenchen.de/T33/research/projects/projects_2001/article_nn3.htm]
    4. “Theoretical modeling of single quantum dot photodiodes”
      M. Sabathil, S. Hackenbuchner, S. Birner, D. Mamaluy, J.A. Majewski
      Annual Report 2001, Walter Schottky Institute, TU Munich (2002)
      [http://www.wsi.tu-muenchen.de/T33/research/projects/projects_2001/article_QDs.htm]
    5. “The influence of the magneto-electric interaction on surface phonon polaritons in insulators”, D. Mamaluy, Ph.D. dissertation, Kharkov, Ukraine, B. Verkin Institute for Low Temperature Physics and Engineering, November 2000.
    6. “Stability analysis of magneto-hydrodynamic processes in industrial aluminum baths”, D. Mamaluy, Master’s Thesis, Kharkov, Ukraine, Kharkov State University, July 1997.

     

    National Conference Proceedings Reviewed Papers, Abstracts and Presentations (since 2003):

    1. IEEE IWCE-16 (International Workshop on Computational Electronics), Nara, Japan, June 4-7, 2013, “Efficient Self-Consistent Quantum Transport Simulator for Quantum Well Devices”, Xujiao Gao, Denis Mamaluy, Nathan Bishop, Malcolm Carroll, Michael Lilly, Richard Muller, Erik Nielsen, Ralph Young.
    2. 13th Advanced Heterostructures and Nanostructures Workshop (AHNW), Hawaii, USA (Dec. 7-12, 2008). “Quantum confinement of gate carriers and nano-scale transistor performance”, D. Mamaluy.
    3. IEEE IWCE-12 (International Workshop on Computational Electronics), UMass, Amherst, October 8-10, 2007. “Can Silicon FinFETs Satisfy ITRS Projections for High Performance 10 nm Devices?”, H. Khan, D. Mamaluy and D. Vasileska.
    4. IEEE IWCE-12 (International Workshop on Computational Electronics), UMass, Amherst, October 8-10, 2007. “Influence of Dimensionality on Quantum Transport in Nano-devices: 3D vs. 2D Modeling”, H. Khan, D. Mamaluy and D. Vasileska.
    5. Second International Conference on Transport Phenomena in Micro and Nanodevices, Il Ciocco Hotel and Conference Center, Barga, Italy, June 11–15, 2006. “Quantum Transport in Nano-scale FinFET Using Contact Block Reduction (CBR) Method”, D. Mamaluy.
    6. IEEE IWCE-11 (International Workshop on Computational Electronics), Vienna University of Technology, Technische Universität Wien, May 25-27, 2006. “Self-consistent Treatment of Quantum Transport in 10 nm FinFET Using Contact Block Reduction (CBR) Method”, H. Khan, D. Mamaluy and D. Vasileska.
    7. Nanotech, Boston, MA, May 7-11, 2006. “Self-consistent quantum-mechanical treatment of the ballistic transport in 10 nm FinFET devices using CBR method”, H. Khan, Mamaluy, Vasileska.
    8. Seventh International Conference on  New  Phenomena in  Mesoscopic Structures/Fifth International Conference on Surfaces and Interfaces of Mesoscopic Devices,Maui, Hawaii, USA, November 27-December 2, 2005. “3D quantum transport simulator for next generation devices”, D. Mamaluy, H. Khan, D. Vasileska.
    9. Second Joint International Conference on New Phenomena in Mesoscopic Systems and Surfaces and Interfaces of Mesoscopic Devices, Nov 27-Dec 2, 2005. “3D quantum transport simulator for next generation devices”, D. Mamaluy, H. Khan, and D. Vasileska.
    10. HCIS-14, Chicago IL, July 24-29, 2005. “Self-Consistent Quantum Mechanical Treatment of the Ballistic Transport in FinFET Devices Using CBR Method”, D. Mamaluy, H. Khan, D. Vasileska.
    11. IEEE IWCE-10, Purdue University, West Lafayette, IN, October 24-27, 2004, “Self-Consistent Contact Block Reduction Method for Ballistic Nanodevices”, D. Mamaluy, D. Vasileska, M. Sabathil, P. Vogl.
    12. Transport Phenomena in Micro and Nanodevices, Ohana Keauhou, Kona Coast, HI, October 17-21, 2004. “Ballistic Quantum Transport Simulations in Nano-Devices”, D. Mamaluy.
    13. 2004 IEEE Silicon Nanoelectronics Workshop, Honolulu, HI, June 13-14, 2004. “Open-system quantum ballistic transport calculation in 10 nm MOSFET device”, D. Mamaluy, D. Vasileska.
    14. First Joint International Conference on New Phenomena in Mesoscopic Systems and Surfaces and Interfaces of Mesoscopic Devices, Wailea Marriot Resort, Maui, HI, Nov 30-Dec 5, 2003. “An efficient method to calculate the ballistic quantum transport and its application to 10 nm MOSFET device”, D. Mamaluy, A. Mannargudi, D. Vasileska.
    15. HCIS-13 (13th International Conference on Nonequilibrium Carrier Dynamics in Semiconductors), Dipartimento di Fisica, UniMoRe, Modena , Italy, July 28 – August 1, 2003. “Contact block reduction method and its application to 25-nm MOSFET device”, D. Mamaluy, D. Vasileska, M. Sabathil and P. Vogl.
    16. IEEE IWCE-9 (International Workshop on Computational Electronics), Monte Porzio Catone, Rome, Italy, 25-28 May, 2003. “Efficient computational method for ballistic current and application to quantum dot RTD's”, M. Sabathil, D. Mamaluy and P. Vogl.

     

    INVITED TALKS

    1. University  of  Massachusetts  Amherst,  Nov.  4-7th,  2009.  “Efficient  Simulation  of  Quantum
      Transport in Nanoelectronic Devices”, D. Mamaluy (invited speaker).
    2. National   Institute   of   Standards   and   Technology   (Gaithersburg,   MD),   June   8th,   2007. "Approaching optimal characteristics of 10 nm Devices: a Quantum Transport Simulation Study of Si FinFET using CBR simulator", D. Mamaluy (invited speaker), H. Khan, D. Vasileska.
    3. Freescale Semiconductor Inc., September 29, 2006, "Efficient modeling of quantum transport in nano-devices", D. Mamaluy (invited speaker), H. Khan, D. Vasileska.
    4. Synopsys Inc., April 28-29, 2005. “3D Quantum Transport Simulator for the Next Generation
      Devices”, D. Mamaluy (invited speaker). Two days of invited lectures at Synopsys Inc.
    5. IEEE  IWCE-10,  International  Workshop  on  Computational  Electronics  (Purdue  University, October 24 – 27, 2004). “Self-Consistent Contact Block Reduction Method for Ballistic Nanodevices”, D. Mamaluy (invited speaker)
    6. Purdue University, July 2004, “Contact Block Reduction method to calculate ballistic quantum transport in nanodevices”, D. Mamaluy (invited speaker).
    7. National Science Foundation, Workshop on Quantum and Many-Body Effects in Nanoscale Devices,  (ASU,   October  24   –   25,   2003).   “CBR   method   for   modeling  nano-devices”, D. Mamaluy (invited speaker)

     

    RESEARCH GRANTS (AWARDED)

    1. (SNL) LDRD “Simulation Capability and Computational Assessment of Memristors as beyond-CMOS logic and memory devices”, Denis Mamaluy (PI), Suzey Gao, Harold Hjalmarson, Matthew Marinella, Patrick Mickel, 10/1/2013-9/30/2016, $1,980,000.
    2. (SNL) Early Career LDRD “A Universal Quantum Transport Computational Capability for Cross-Technology Comparisons of Beyond-CMOS Nanodevices”, Denis Mamaluy (PI), Suzey Gao, Michael Lilly, 10/1/2012-9/30/2014, $500,000.
    3. (ASU) Science Foundation Arizona (SFAz), Competitive Advantage Award, “Heterostructure Nanowire Simulation for Robust Manufacturing”, D. Mamaluy (PI), 9/1/2008-8/31/2009, $133,000
    4. (ASU) National Science Foundation, Collaborative Research: “Quantum Simulator for Modeling Quantum Dot Photodetectors”, D. Mamaluy (ASU), D. Vasileska (ASU), G. Klimeck (Purdue University), 5/1/2007-4/30/2010, $165,000.
    5. (ASU) Office of Naval Research AWARD No.: N000140610094 “3D Quantum Simulator for Nano-Device Modeling and Performance Evaluation”, D. Vasileska (PI), D. Mamaluy (co-PI), 10/1/2005-9/30/2008, $380,000.

     

    PROFESSIONAL AND SCIENTIFIC SERVICE

    Scientific and Professional Society Memberships and Activities:

    • IEEE Senior Member (since 2012), Member (since 2005)
    • IEEE Electron Devices Society Senior Member (since 2012), Member (since 2005)

     

    JOURNAL REFEREE SERVICE

    • IEEE Transactions on Electron Devices (named in the Golden List of Reviewers, 2007-2010)
    • Journal of Applied Physics
    • Journal of Computational Electronics
    • Microelectronic Engineering


    PROPOSAL REVIEWER SERVICE

    • Sandia National Laboratories LDRD panel
    • Austrian Science Fund (FWF)
    • National Science Foundation (invited panel reviewer in Dec. 2006, May 2010, Dec. 2010)
    • Research Councils in Great Britain (via FWF)

     

    SYNERGISTIC ACTIVITIES

    • Creation and development of the Contact Block Reduction (CBR) method for quantum transport simulation in nano-structures and nano-devices.
    • Development of one the fastest1and most accurate2 within its class quantum transport simulators for nano-devices. The simulator allowed to perform, for the first time, full- scale optimization3 and process variation analysis4 of a novel, energy efficient 10-nm FinFET device that satisfies ITRS specifications for high-performance, high-efficiency 10-nm gate length devices.

     

    COLLABORATORS AND OTHER AFFILIATIONS

    1. Collaborators (external to SNL):
      S. Goodnick (ASU), D. Ferry (ASU), M. Fischetti (UMass Amherst), O. Hartin (Freescale Semicon. Inc.), G. Klimeck (NCN, Purdue), S. Laux (IBM), Eric Polizzi (UMass Amherst), M. Sabathil (Osram), D. Vasileska (ASU), P. Vogl (Walter Shottky Institute), N. Zimmerman (NIST).
    2. Graduate advisors of Denis Mamaluy:
      Graduate advisor: A. M. Ermolaev, Kharkov State University, Ukraine.
      Ph. D. study and thesis advisor: I. E. Chupis, ILTPE, Kharkov, Ukraine.
    3. Denis Mamaluy is the thesis adviser and post-graduate scholar sponsor for:
      Ph.D.: Hasanur Khan (graduated Nov. 2007, now is a nanodevice researcher at Intel)

     

    SCIENTIFIC HONORS (AWARDS)

    • The Best Poster Presentation - 7th International Conference on Complex Media (Bianisotropics
      ‘98) “New types of surface polaritons in ferroelectrics induced by magnetoelectric interaction”, D. A. Mamaluy and I. E. Chupis. Braunschweig, Germany, 1998.
    • The Diploma with Honors, M.S. in Physics, Kharkov State University, Ukraine, 1997.

     

    LANGUAGES

    Russian (fluent), German (basic), Greek (basic).

     


    1. ”Simulation of quantum transport in double‐gate MOSFETs using the non‐equilibrium Green’s function formalism in real‐space: A comparison of four methods”, Yasser M. Sabry et al., Int. J. Numer. Model. (2010), DOI: 10.1002/jnm.780.
    2. “High‐Order Element Effects of the Green’s Function in Quantum Transport Simulation of Nanoscale Devices”, Hao
      Wang, Gaofeng Wang, Sheng Chang, Qijun Huang, IEEE T‐ED Vol. 56, No. 12, pp. 3106‐3114 (2009).
    3. “Approaching Optimal Characteristics of 10 nm High Performance Devices: a Quantum Transport Simulation Study
      of Si FinFET”, H. Khan, D. Mamaluy and D. Vasileska, IEEE T‐ED Vol. 55, pp. 743‐753 (2008).
    4. “Simulation of the Impact of Process Variation on the Optimized 10‐nm FinFET”, H. Khan, D. Mamaluy, D.
      Vasileska, IEEE Trans El. Dev. 55, pp. 2134‐2141 (2008).

    Denis Mamaluy

    Contact Me

  • Email: mamaluy@sandia.gov
  • Phone: 505-844-2054
  • FAX: 505-284-2518
  • Office CSRI/176
  • Maps/Driving instructions
  • Mailing Address:

    Advanced Device Technologies Department
    Sandia National Labs
    P.O. Box 5800, Mail Stop 1322
    Albuquerque, NM 87185-1322

    Mail that needs a street address
    (e.g. express mail/Fed Ex):

    Sandia National Laboratories
    Building CSRI/270
    1515 Eubank SE
    Albuquerque, NM 87123-1319